1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a latch circuit and a flip-flop circuit retaining data.
2. Description of the Background Art
FIG. 9 is a circuit diagram showing a structure of a conventional flip-flop circuit described in IEICE TRANSACTIONS on Electronics, vol. E78-C, No. 12, December 1995, pp. 1746-1753.
Referring to FIG. 9, the flip-flop circuit includes transmission gates TG1-TG8, inverter gates INV1-INV4, a first data input terminal DI, a second data input terminal DIB, a first clock input terminal CK, a second clock input terminal CKB, a first data output terminal DO, and a second data output terminal DOB. Each of the transmission gates TG1-TG8 is constructed of a set of P channel MOS transistor and N channel MOS transistor connected in parallel.
FIG. 10 is a circuit diagram showing a structure of each of the inverter gates INV1-INV4 shown in FIG. 9. As shown in FIG. 10, the inverter gate includes a supply voltage node VDD, a data input terminal IN, a data output terminal OUT, a P channel MOS transistor connected between supply voltage node VDD and data output terminal OUT and having its gate connected to data input terminal IN, a ground node, and an N channel MOS transistor connected between the ground node and data output terminal OUT and having its gate connected to data input terminal IN.
The inverter gate outputs, data at a high level (supply voltage) if data supplied to data input terminal IN is less than a logic threshold voltage of the inverter gate (generally an intermediate voltage between supply voltage and ground voltage), and data at a low level (ground voltage) if data supplied to data input terminal IN is more than the logic threshold voltage of the inverter gate, to data output terminal OUT.
An operation of the flip-flop circuit shown in FIG. 9 is next described referring to timing charts of FIGS. 11A-11C.
At time T1, a signal at the high level is applied to the first data input terminal DI, and a signal at the low level is applied to the second data input terminal DIB. Those signals applied to the first and second data input terminals DI and DIB are here supposed to be first data DATA1. At this time, when a signal at the high level and a signal at the low level are respectively supplied to the first and second clock input terminals CK and CKB, transmission gates TG1 and TG2 are turned off and transmission gates TG3-TG6 are turned on. Transmission gates TG7 and TG8 are turned off.
At time T2, if the signal supplied to the first clock input terminal CK goes down to the low level, and the signal supplied to the second clock input terminal CKB attains the high level, transmission gates TG1 and TG2 are turned on, an output from inverter gate INV2 is set to the low level by the high level signal supplied to the first data input terminal DI, and an output from inverter gate INV1 is set to the high level by the low level signal supplied to the second data input terminal DIB. At this time, transmission gates TG3-TG6 are turned off and transmission gates TG7 and TG8 are turned on.
At time T3, the signal supplied to the first data input terminal DI goes down to the low level, and the signal supplied to the second data input terminal DIB goes up to the high level. These signals are here supposed to be second data DATA2. Simultaneously, the signal supplied to the first clock input terminal CK attains the high level and the signal supplied to the second clock input terminal CKB goes down to the low level at time T3. Consequently, the second data DATA2 applied to the first and second data input terminals DI and DIB is separated from an internal circuit since transmission gates TG1 and TG2 are turned off. At this time, transmission gates TG3 and TG4 are turned on, the low level signal output from inverter gate INV2 is supplied to inverter gate INV1 via transmission gate TG4, and the high level signal output from inverter gate INV1 is supplied to inverter gate INV2 via transmission gate TG3. Consequently, the first data DATA1 supplied to the first and second data input terminals DI and DIB is retained by a closed loop latch circuit constituted of inverter gate INV1, transmission gate TG3, inverter gate INV2, and transmission gate TG4. Since transmission gates TG5 and TG6 are also turned on at this time, an output signal of inverter gate INV1 is supplied to inverter gate INV4 via transmission gate TG5, and an output signal of inverter gate INV2 is supplied to inverter gate INV3 via transmission gate TG6.
As a result, the first and second data output terminals DO and DOB output the first data DATA1 at time T3.
At time T4, when the signal supplied to the first clock input terminal CK goes down to the low level and the signal supplied to the second clock input terminal CKB attains the high level, transmission gates TG1 and TG2 are turned on. Consequently, transmission gates TG1 and TG2 set the output node of inverter gate INV1 to the low level, and the output node of inverter gate INV2 to the high level. The second data DATA2 is thus taken. At this time, transmission gates TG3-TG6 are turned off and transmission gates TG7 and TG8 are turned on. Accordingly, the first and second data output terminals DO and DOB continuously output the first data DATA1, while the first data DATA1 is retained by a closed loop latch circuit constituted of inverter gate INV3, transmission gate TG7, inverter gate INV4 and transmission gate TG8.
The flip-flop circuit shown in FIG. 9 has a function, as described above, of receiving data signals supplied to the first and second data input terminals DI and DIB in synchronism with clock signals applied to the first and second clock input terminals CK and CKB, temporarily retaining the data signals, and outputting the data signals from the first and second data output terminals with phase therebetween shifted.
According to the description above, the signal supplied to the first data input terminal DI changes its state from the high level to the low level, and the signal changing its state from the low level to the high level is supplied to the second data input terminal DIB to which an inverted signal of the signal applied to the first data input terminal DI is supplied (an operation from the time T1 to the time T5). However, the flip-flop circuit similarly operates from the time T5 to the time T7 regardless of change in signal level.
FIG. 12 is a circuit diagram illustrating a structure of a conventional latch circuit. The flip-flop circuit shown in FIG. 9 is structured by serially connecting such latch circuits in two stages. As shown in FIG. 12, the latch circuit includes transmission gates TG1-TG4, inverter gates INV1 and INV2, a first data input terminal DI, a second data input terminal DIB, a first clock input terminal CK, a second clock input terminal CKB, a first data output terminal DO, and a second data output terminal DOB.
An operation of the latch circuit is described referring to timing charts of FIGS. 13A-13C. Referring to FIG. 13A, at time T1, a high level signal is supplied to the first data input terminal DI, and a low level signal is supplied to the second data input terminal DIB. The signals supplied to the first and second data input terminals DI and DIB are herein supposed to be first data DATA1. At this time, if a high level signal is supplied to the first clock input terminal CK and a low level signal is supplied to the second clock input terminal CKB, transmission gates TG1 and TG2 are turned off and transmission gates TG3 and TG4 are turned on.
Referring to FIG. 13B, at time T2, if the signal applied to the first clock input terminal CK goes down to the low level and the signal supplied to the second clock input terminal CKB goes up to the high level, transmission gates TG1 and TG2 are turned on, the high level signal applied to the first data input terminal DI allows an output node of inverter gate INV2 or the second data output terminal DOB to have voltage at the low level, and the low level signal supplied to the second data input terminal DIB allows an output node of inverter gate INV1 or the first data output terminal DO to have voltage at the high level. Accordingly, the first and second data output terminals DO and DOB output the first data DATA1 as shown in FIG. 13C. At this time, transmission gates TG3 and TG4 are turned off.
As shown in FIG. 13A, at time T3, the signal supplied to the first data input terminal DI goes down to the low level and the signal supplied to the second data input terminal DIB goes up to the high level. The signals applied to the first and second data input terminals DI and DIB are herein supposed to be second data DATA2. At time T3, as shown in FIG. 13B, the signal supplied to the first clock input terminal CK attains the high level and the signal supplied to the second clock input terminal CKB goes down to the low level. Consequently, the second data DATA2 supplied to the first and second data input terminals DI and DIB is separated from an internal circuit since transmission gates TG1 and T2 are turned off. At time T3, transmission gates TG3 and TG4 are turned on. Accordingly, a low level signal output from inverter gate INV2 is supplied to inverter gate INV1 via transmission gate TG4, and a high level signal output from inverter gate INV1 is supplied to inverter gate INV2 via transmission gate TG3. As a result, a closed loop latch circuit constituted of inverter gate INV1, transmission gate TG3, inverter gate INV2 and transmission gate TG4 latches the first data DATA1 supplied to the first and second data input terminals DI and DIB, while the first and second data output terminals DO and DOB continuously output the data.
At time T4, when the signal supplied to the first clock input terminal CK goes down to the low level and the signal supplied to the second clock input terminal CKB goes up to the high level, transmission gates TG1 and TG2 are turned on, the output node of inverter gate INV2 attains the high level, and the output node of inverter gate INV1 goes down to the low level.
Accordingly, a low level signal is output from the first data output terminal DO, and a high level signal is output from the second data output terminal DOB. In other words, the second data DATA2 is output.
The latch circuit has a function of, as described above, receiving data signals supplied to the first and second data input terminals DI and DIB synchronously with clock signals supplied to the first and second clock input terminals CK and CKB, and outputting the data signals from the first and second data output terminals DO and DOB with phase therebetween shifted. According to the description above, the signal supplied to the first data input terminal DI changes its state from the high level to the low level, and the signal changing its state from the low level to the high level is supplied to the second data input terminal DIB to which an inverted signal of the signal supplied to the first data input terminal DI is applied (time T1-time T4). However, the latch circuit similarly operates after time T4.
Both of the flip-flop circuit and the latch circuit described above have a function of receiving the data signals synchronously with the clock signals and outputting them with phase shifted. However, the phase between the data signals output from the latch circuit is shifted, compared with that of the flip-flop circuit, by 1/2 period of the clock signals.
FIG. 14 shows a structure of a circuit which buffers a clock signal or a data signal supplied to the flip-flop circuit shown in FIG. 9 or the latch circuit shown in FIG. 12. Referring to FIG. 14, the circuit includes a signal input terminal CIN, an inverter gate INV5 connected to signal input terminal CIN, a second output terminal CKOB connected to inverter gate INV5, an inverter gate INV6 connected to inverter gate INV5, and a first output terminal CKO connected to inverter gate INV6.
When a high level signal is applied to signal input terminal CIN, a high level signal is output from the first output terminal CKO via inverter gates INV5 and INV6, and a low level signal is output from the second output terminal CKOB via inverter gate INV5.
When a low level signal is input to signal input terminal CIN, a low level signal is output from the first output terminal CKO, and a high level signal is output from the second output terminal CKOB.
The circuit thus generates two signals complementary to each other based on one input signal. Signals generated by the buffer circuit are respectively supplied to the first data input terminal DI, the second data input terminal DIB, the first clock input terminal CK, and the second clock input terminal CKB of the flip-flop circuit shown in FIG. 9 or the latch circuit shown in FIG. 12. If the buffer circuit is used for the clock signals, the output terminals of the buffer circuit are connected to four P channel MOS transistors and four N channel MOS transistors of the flip-flop circuit, or the output terminals are connected to two P channel MOS transistors and two N channel MOS transistors of the latch circuit.
The flip-flop circuit shown in FIG. 9 has twelve (12) P channel MOS transistors and twelve (12) N channel MOS transistors, and the latch circuit shown in FIG. 12 has six (6) P channel MOS transistors and six (6) N channel MOS transistors. Therefore, a disadvantage thereof is a large occupied area of a circuit.
In addition, when the buffer circuit is used for the clock signals, two output terminals of the buffer circuit are connected to four P channel MOS transistors and four N channel MOS transistors of the flip-flop circuit, or connected to two P channel MOS transistors and two N channel MOS transistors of the latch circuit as described above. Problems in these cases are that a large load capacitance of the output terminal and a highly large power consumed by the buffer circuit used for the clock signals for charging and discharging of the load capacitance.